Introduction to 8051 microcontroller

Table of Contents:-
1. Features of 8051 Microcontroller
2. Pin configuration
3. 8051 Memory Architecture
4. Timer Description
5. Interrupts in 8051
6. Serial Communication in 8051
7. Applications of Microcontroller
8. Comparison between Pentium and 8051

1. Features of 8051 µcontroller

The 8051 architecture consists of these specific features:
-16 bit PC &data pointer (DPTR)
-8 bit program status word (PSW)
-8 bit stack pointer (SP)
-Internal ROM(FLASH) 4k
-Internal RAM of 128 bytes.
-4 register banks, each containing 8 registers
-80 bits of general purpose data memory
-32 input/output pins arranged as four 8 bit ports: P0-P3
-Two 16 bit timer/counters: T0-T1
-Two external and three internal interrupt sources Oscillator and clock circuits.
-a five vector two-level interrupt architecture
-a full duplex serial port,
-on-chip oscillator
-clock circuitry.

2. Pin Diagram and Pin Functions

The pin diagram of the 8051 shows all of the input/output pins unique to microcontrollers:

The following are some of the capabilities of 8051 microcontroller.
-Internal ROM and RAM
-I/O ports with programmable pins
-Timers and counters
-Serial data communication
ALE/PROG:

Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory.
ALE is emitted at a constant rate of 1/6 of the oscillator frequency, for external timing or clocking purposes, even when there are no accesses to external memory. (However, one ALE pulse is skipped during each access to external Data Memory.)
This pin is also the program pulse input (PROG) during EPROM programming.

PSEN:

Program Store Enable is the read strobe to external Program Memory.
When the device is executing out of external Program Memory, PSEN is activated twice each machine cycle (except that two PSEN activations are skipped during accesses to external Data Memory).
PSEN is not activated when the device is executing out of internal Program Memory

EA/VPP:

When EA is held high the CPU executes out of internal Program.
Holding EA low forces the CPU to execute out of external memory regardless of the Program Counter value.
In the EPROM devices, this pin also receives the programming supply voltage (VPP) during EPROM programming.

XTAL1:

Input to the inverting oscillator amplifier.

XTAL2:

Output from the inverting oscillator amplifier.

1. Port 0:

Port 0 is an 8-bit open drain bidirectional port.
As an open drain output port, it can sink eight LS TTL loads.
Port 0 pins that have 1s written to them float, and in that state will function as high impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to external memory.
In this application it uses strong internal pullups when emitting 1s.
Port 0 emits code bytes during program verification. In this application, external pullups are required.

2. Port 1:

Port 1 is an 8-bit bidirectional I/O port with internal pullups.
Port 1 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs.
As inputs, port 1 pins that are externally being pulled low will source current because of the internal pullups.

3. Port 2:

Port 2 is an 8-bit bidirectional I/O port with internal pullups.
Port 2 emits the high-order address byte during accesses to external memory that use 16-bit addresses. In this application, it uses the strong internal pullups when emitting 1s.

4. Port 3:

Port 3 is an 8-bit bidirectional I/O port with internal pullups.
It also serves the functions of various special features of the 80C51 Family as follows:

Port Pin                 Alternate Function
P3.0             RxD                     (serial input port)
P3.1            TxD                     (serial output port)
P3.2             INT0                    (external interrupt 0)
P3.3            INT1 (external interrupt 1)
P3.4             T0 (timer 0 external input)
P3.5             T1 (timer 1 external input)
P3.6             WR (external data memory write strobe)
P3.7             RD                      (external data memory read strobe)

The alternate functions can only be activated if the corresponding bit latch in the port SFR contains a 1. Otherwise the port pin remains at 0.

* All four ports in the 80C51 are bidirectional. Each consists of a latch (Special Function Registers P0 through P3), an output driver, and an input buffer.

* The output drivers of Ports 0 and 2, and the input buffers of Port 0, are used in accesses to external memory. In this application, Port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue to emit the P2 SFR content.

Reset requirements

The process of starting any microcontroller is a non-trivial one. The underlying hardware is complex and a small, manufacturer-defined, ‘reset routine’ must be run to place this hardware into an appropriate state before it can begin executing the user program. Running this reset routine takes time, and requires that the microcontroller’s oscillator is operating.

Where your system is supplied by a robust power supply, which rapidly reaches its specified output voltage when switched on, rapidly decreases to 0V when switched off, and – while switched on – cannot ‘brown out’ (drop in voltage), then you can safely use low-cost reset hardware based on a capacitor and a resistor to ensure that your system will be reset correctly: this form of reset circuit is shown in Figure 2.3a.
Where your power supply is less than perfect, and / or your application is safety related, the simple RC solution will not be suitable. Several manufacturers provide more sophisticated reset chips which may be used in these circumstances

Clock frequency and performance

All digital computer systems are driven by some form of oscillator circuit: the 8051 is certainly no exception.The oscillator circuit is the ‘heartbeat’ of the system and is crucial to correct operation. For example, if the oscillator fails, the system will not function at all; if the oscillator runs irregularly, any timing calculations performed by the system will be inaccurate.

We consider some important issues linked to oscillator frequency and performance in this section :
a) The link between oscillator frequency and machine-cycle period
One of the first questions to be asked when considering a microcontroller for a project is whether it has the required level of performance. As a general rule, the speed at which your application runs is directly determined by the oscillator frequency: in most cases, if you double the oscillator frequency, the application will run twice as fast. When we want to compare different processors, we need a way of specifying performance in a quantitative manner. One popular measure is the number of machine instructions that may be executed in one second, usually expressed in ‘MIPS’ (Million Instructions Per Second). For example, in the original Intel 8051 microcontroller, a minimum of 12 oscillator cycles was required to execute a machine instruction. The original 8051 had a maximum oscillator frequency of 12 MHz and therefore a peak performance of 1 MIP.

A simple way of improving the 8051 performance is to increase the clock frequency. More modern (Standard) 8051 devices allow the use of clock speeds well beyond the 12 MHz limit of the original devices. For example, the Atmel AT89C55WD, allow clock speeds up to 33 MHz: this raises the peak performance to around 3 MIPS.

Another way of improving the performance is to make internal changes to the microcontroller so that fewer oscillator cycles are required to execute each machine instruction. The Dallas ‘High Speed Microcontroller’ devices (87C520, and similar) use this approach, so that only four oscillator cycles are required to execute a machine instruction. These Dallas devices also allow faster clock rates (typically up to 33 MHz). Combined, these changes give a total performance of around 8 MIPS. Similar changes are made in members of the Winbond family of Standard 8051 devices (see the Winbond W77E58, for example) resulting in performance figures of up to 10 MIPS.

Clearly, for maximum performance, we would like to execute instructions at a rate of one machine instruction per oscillator cycle. For example, the Dallas ‘Ultra High Speed’ 89C420 operates at this rate: as a result, it runs at 12 times the speed of the original 8051. In addition, the 89c420 can operate at up to 50 MHz, increasing overall performance to around 40–50 MIPS.

To put all these figures in perspective, a modern desktop PC has a potential performance of around 1000 MIPS. However, a good percentage of this performance (perhaps 50% or more) will be ‘consumed’ by the operating system. By contrast, the embedded operating system we will describe in Chapter 7 consumes less than 1% of the processor resources of the most basic 8051: this leaves sufficient CPU cycles to run a complex embedded application.
b) Why you should choose a low oscillator frequency
In our experience, many developers select an oscillator frequency that is at or near the maximum value supported by a particular device. For example, the Infineon C505/505C will operate with crystal frequency of 2–20 MHz, and many people automatically choose values at or near the top of this range, in order to gain maximum performance.

This can be a mistake, for the following reasons:
- Many applications do not require the levels of performance that a modern 8051 device can provide.
- In most modern (CMOS-based) 8051s, there is an almost linear relationship between the oscillator frequency and the power supply current. As a result, by using the lowest frequency necessary it is possible to reduce the power requirement: this can be useful, particularly in battery-powered applications.
- When accessing low-speed peripherals (such as slow memory, or liquid-crystal displays), programming and hardware design can be greatly simplified – and the cost of peripheral components, such as memory latches, can be reduced – if the chip is operating more slowly.
- The electromagnetic interference (EMI) generated by a circuit increases with
clock frequency.

In general, you should operate at the lowest possible oscillator frequency compatible with the performance needs of your application. As we will see in later chapters, simulating the processor is a good way of determining the required operating frequency for a particular application.

3. Memory Organization in 8051

The 8051 has a separate memory space for code (programs) and data. We will refer here to on-chip memory and external memory as shown in below figure. In an actual implementation the external memory may, in fact, be contained within the microcomputer chip. However, we will use the definitions of internal and external memory to be consistent with 8051 instructions which operate on memory. Note, the separation of the code and data memory in the 8051 architecture is a little unusual.

The separated memory architecture is referred to as Harvard architecture whereas Von Neumann architecture defines a system where code and data can share common memory.

External Code Memory

The executable program code is stored in this code memory. The code memory size is limited to 64KBytes (in a standard 8051). The code memory is read-only in normal operation and is programmed under special conditions e.g. it is a PROM or a Flash RAM type of memory.

External RAM Data Memory

This is read-write memory and is available for storage of data. Up to 64KBytes of external RAM data memory is supported (in a standard 8051).

Internal Memory

The 8051’s on-chip memory consists of 256 memory bytes organized as follows:

First 128 bytes:

00h to 1Fh Register Banks

20h to 2Fh Bit Addressable RAM

30 to 7Fh General Purpose RAM

Next 128 bytes:

80h to FFh Special Function Registers

Advantages

Simultaneous access to Program and Data store

8-bit address space extended to 256+128 = 384 registers by distinguishing between direct and indirect addressing for upper 128 bytes. Good for code compression

Bit addressable great for managing status flags

Disadvantage

A little bit confusing, with potential for errors

4. Timer

This shows how timer overflows and when it gets reset automatically on reaching 65536 maximum value
When the Timer reaches FFFFH, it reloads to 0000H. This roll over is communicated to the controller by rising a flag corresponding to that Timer, i.e., a flag bit is raised (set high) when the timer starts counting from 0000H again. TF0 and TF1 are the Timer flags corresponding to Timers 0 and 1. These flags must be cleared (set low) by software every time they are raised. The Timer may terminate updating register values after a roll over or continue with its operation.

Starting or stopping a Timer

For every Timer, there is a corresponding Timer control bit which can be set or cleared by the program to start or stop the Timer. TR0 and TR1 are the control bits for Timers 0 and 1 respectively. Setting the control bit would start the Timer.

TR0 = 1;         starts Timer 0

TR1 = 1;         starts Timer 1

Clearing the control bit would stop the Timer.

TR0 = 0;         stops Timer 0

TR1 = 0;         stops Timer1

4.1 MODES OF TIMER

There are four Timer modes designated as Modes 0, 1, 2 and 3. A particular mode is selected by configuring the M1 & M0 bits of TMOD register.

13-bit Time Mode (mode 0)

Mode 0 is a 13 bit Timer mode and uses 8 bits of high byte and 5 bit prescaler of low byte. The value that the Timer can update in mode0 is from 0000H to 1FFFH. The 5 bits of lower byte append with the bits of higher byte. The Timer rolls over from 1FFFH to 0000H to raise the Timer flag.

Timer mode "0" is a 13-bit timer. This is a relic that was kept around in the 8051 to maintain compatibility with its predecessor, the 8048. Generally the 13-bit timer mode is not used in new development.

When the timer is in 13-bit mode, TLx will count from 0 to 31. When TLx is incremented from 31, it will "reset" to 0 and increment THx. Thus, effectively, only 13 bits of the two timer bytes are being used: bits 0-4 of TLx and bits 0-7 of THx. This also means, in essence, the timer can only contain 8192 values. If you set a 13-bit timer to 0, it will overflow back to zero 8192 machine cycles later.

Again, there is very little reason to use this mode and it is only mentioned so you wont be surprised if you ever end up analyzing archaic code which has been passed down through the generations (a generation in a programming shop is often on the order of about 3 or 4 months).

16-bit Time Mode (mode 1)

Mode1 is one of the most commonly used Timer modes. It allows all 16 bits to be used for the Timer and so it allows values to vary from 0000H to FFFFH.

If a value, say YYXXH, is loaded into the Timer bytes, then the delay produced by the Timer will be equal to the product:

[(FFFFH – YYXXH +1) x (period of one timer clock)].

It can also be considered as follows: convert YYXXH into decimal, say NNNNN, then delay will be equal to the product:

[(65536-NNNNN) x (period of one timer clock)].

The period of one timer clock is 1.085 µs for a crystal of 11.0592 MHz frequency as discussed above.

Timer mode "1" is a 16-bit timer. This is a very commonly used mode. It functions just like 13-bit mode except that all 16 bits are used.

TLx is incremented from 0 to 255. When TLx is incremented from 255, it resets to 0 and causes THx to be incremented by 1. Since this is a full 16-bit timer, the timer may contain up to 65536 distinct values. If you set a 16-bit timer to 0, it will overflow back to 0 after 65,536 machine cycles.

Timer mode "1" is a 16-bit timer. This is a very commonly used mode. It functions just like 13-bit mode except that all 16 bits are used.

TLx is incremented from 0 to 255. When TLx is incremented from 255, it resets to 0 and causes THx to be incremented by 1. Since this is a full 16-bit timer, the timer may contain up to 65536 distinct values. If you set a 16-bit timer to 0, it will overflow back to 0 after 65,536 machine cycles.

8-bit Time Mode (mode 2)

Timer mode "2" is an 8-bit auto-reload mode. What is that, you may ask? Simple. When a timer is in mode 2, THx holds the "reload value" and TLx is the timer itself. Thus, TLx starts counting up. When TLx reaches 255 and is subsequently incremented, instead of resetting to 0 (as in the case of modes 0 and 1), it will be reset to the value stored in THx.

Whats the benefit of auto-reload mode? Perhaps you want the timer to always have a value from 200 to 255. If you use mode 0 or 1, youd have to check in code to see if the timer had overflowed and, if so, reset the timer to 200. This takes precious instructions of execution time to check the value and/or to reload it. When you use mode 2 the microcontroller takes care of this for you. Once youve configured a timer in mode 2 you dont have to worry about checking to see if the timer has overflowed nor do you have to worry about resetting the value--the microcontroller hardware will do it all for you.

The auto-reload mode is very commonly used for establishing a baud rate which we will talk more about in the Serial Communications chapter.

Split Timer Mode (mode 3)

Timer mode "3" is a split-timer mode. When Timer 0 is placed in mode 3, it essentially becomes two separate 8-bit timers. That is to say, Timer 0 is TL0 and Timer 1 is TH0. Both timers count from 0 to 255 and overflow back to 0. All the bits that are related to Timer 1 will now be tied to TH0.

While Timer 0 is in split mode, the real Timer 1 (i.e. TH1 and TL1) can be put into modes 0, 1 or 2 normally--however, you may not start or stop the real timer 1 since the bits that do that are now linked to TH0. The real timer 1, in this case, will be incremented every machine cycle no matter what.

The only real use I can see of using split timer mode is if you need to have two separate timers and, additionally, a baud rate generator. In such case you can use the real Timer 1 as a baud rate generator and use TH0/TL0 as two separate timers.

5. Interrupts

An interrupt causes a temporary diversion of program execution in a similar sense to a program subroutine call, but an interrupt is triggered by some event, external to the currently operating program. We say the interrupt event occurs asynchronously to the currently operating program as it is not necessary to know in advance when the interrupt event is going to occur.

5.1 8051 Interrupts

There are five interrupt sources for the 8051. Since the main RESET input can also be considered as an interrupt, six interrupts can be listed as follows:

Flag	Vector Address
RST	0000H
IE0	0003H
TF0	000BH
IE1	0013H
TF1	001BH
RI or TI	0023H

We will concentrate on the external interrupts for now, and later we will examine the other interrupt sources. Here’s a brief look at some of the register bits which will be used to set up the interrupts in the example programs.

The Interrupt Enable, IE, register is an SFR register at location A8h in Internal RAM. The EA bit will enable all interrupts (when set to 1) and the individual interrupts must also be enabled.

Interrupt Enable register

ET1EX1

ET0

EX0

For example, if we want to enable the two external interrupts we would use the instruction:

MOV IE, #10000101B

Each of the two external interrupt sources can be defined to trigger on the external signal, either on a negative going edge or on a logic low level state. The negative edge trigger is usually preferred as the interrupt flag is automatically cleared by hardware, in this mode. Two bits in the TCON register are used to define the trigger operation. The TCON register is another SFR register and is located at location 88h in Internal RAM. The other bits in the TCON register will be described later in the context of the hardware Timer/Counters.
To define negative edge triggering for the two external interrupts use instructions as follows:

SETB IT0; negative edge trigger for interrupt 0

SETB IT1; negative edge trigger for interrupt 1

Figure 6.1 shows the flow of operation when a system is interrupted. In the example it is assumed that some program, say the main program, is executing when the external interrupt INT0 occurs. The 8051 hardware will automatically complete the current machine level (assembler level) instruction and save the Program Counter to the stack. The IE register is also saved to the stack. The IE0 flag is disabled (cleared) so that another INT0 interrupt will be inhibited while the current interrupt is being serviced. The Program Counter is now loaded with the vector location 0003h. This vector address is a predefined address for interrupt INT0 so that program execution will always trap to this address when an INT0 interrupt occurs. Other interrupt sources have uniquely defined vector addresses for this purpose. The set of these vector addresses is referred to as the interrupt vector table. Program execution is now transferred to address location 0003h. In the example a LJMP instruction is programmed at this address to cause the program to jump to a predefined start address location for the relevant ISR (Interrupt Service Routine) routine. The ISR routine is a user written routine, which defines what action is to occur following the interrupt event. It is good practice to save (PUSH) to the stack any registers used during the ISR routine and to restore (POP) these registers at the end of the ISR routine, thus preserving the registers’ contents, just like a register is preserved within a subroutine program. The last instruction in the ISR routine is a RETI (RETurn from Interrupt) instruction and this instruction causes the 8051 to restore the IE register values, enable the INT0 flag, and restore the Program Counter contents from the stack.

Since the Program Counter now contains the address of the next instruction which was to be executed before the INT0 interrupt occurred, the main program continues as if it had never being interrupted. Thus only the temporal behavior of the interrupted program has been affected by the interrupt; the logic of the program has not been otherwise affected.

5.2 EXAMPLE INTERRUPT DRIVEN PROGRAM

Figure shows and oven control system where a heating oven, as part of a manufacturing process, is to be controlled within the temperature range, between 190oC and 200 oC . An 8051 microcomputer based system is used to control the temperature. The oven has two built-in temperature sensors. The low threshold sensor outputs logic 0 if the temperature is below 190 oC, otherwise it outputs a logic high level (say 5 volts). The high threshold sensor outputs a logic low level if the temperature exceeds 200 oC, otherwise it outputs a logic high level. The temperature sensors are connected to the 8051’s interrupt inputs, INT0 and INT1, as shown in the diagram. Both of these interrupt inputs are set to trigger at negative voltage transitions. The microcomputer outputs logic 1 on the P1.0 output pin to turn on the heater element and it outputs logic 0 to turn off the heating element. Assume the necessary hardware driver circuitry, to switch power to the oven, is included in the oven.

The microcomputer’s program is written so that an interrupt from the low threshold sensor will cause the heating element to turn on and interrupt from the high threshold sensor will cause the heating element to turn off.

6. 8051 Serial Communication

RS-232 Serial Communications

The EIA RS-232 serial communication standard is a universal standard, originally used to connect teletype terminals to modem devices. Figure 6.1(a) shows a PC connected to a device such as a modem or a serial printer using the RS-232 connection. In a modern PC the RS-232 interface is referred to as a COM port. The COM port uses a 9-pin D-type connector to attach to the RS-232 cable. The RS-232 standard defines a 25-pin D-type connector but IBM reduced this connector to a 9-pin device so as to reduce cost and size.

Figure 6.1(b) shows a simple simplex serial communication link where data is being transmitted serially from left to right. A single Tx (transmit) wire is used for transmission and the return (Gnd) wire is required to complete the electrical circuit.

Figure 6.1(c) shows the inclusion of another physical wire to support full-duplex (or half-duplex) serial communication. The RS-232 (COM port) standard includes additional signal wires for “hand-shake” purposes, but the fundamental serial communication can be achieved with just two or three wires as shown.

The serial data is transmitted at a predefined rate, referred to as the baud rate. The term baud rate refers to the number of state changes per second which is the same as the bit rate for this particular communication scheme. Typical baud rates are: 9600 bps; 19,200 bps; 56kbps etc.

Asynchronous Serial Communications

Since data is sent is a serial fashion, without any reference to a timing clock to help synchronise the receiver clock in terms of frequency and phase, the system is said to be non-synchronous, or asynchronous. The baud rate clocks at each end of the RS-232 link are set to the same frequency values but there is no mechanism to synchronize these clocks. Figure 6.2(a) shows three bytes transmitted by the PC. Assume the bytes are ascii coded to represent the characters A, B and C. The receiver needs to know exactly where each character starts and finishes. To achieve this the data character is framed with a start bit at the beginning of each character and a stop bit at the end of each character. Figure 6.2(b) shows the start bit as a low logic level and the stop bit as high logic level. Thus the receiver can detect the start bit and it then clocks in the character bits. The receiver then expects to find the stop bit, existing as logic high bit. This is a crude form of synchronization applied to a system which is inherently non-synchronous. A high price is paid for this form of synchronization in terms of bandwidth, as for every eight bits of data transmitted two bits are required to support the framing. Ten bits are transmitted to support eight bits of data thus the scheme is, at best, just eighty percent efficient.

6.1 INTERNAL STRUCTURE OF 8051 TO SUPPORT SERIAL COMMUNICATION

Since serial is asynchronous; the port is able to transmit data on one line while receiving data on another. Other lines are available for handshaking, but are not required. The important serial characteristics are baud rate, data bits, stop bits, and parity. For two ports to communicate, these parameters must match.

8051 has an integrated UART, also known as SERIAL PORT. The fact that the 8051 has an integrated serial port means that you may very easily read and write values to the serial port. If it were not for the integrated serial port, writing a byte to a serial line would be a rather tedious process requiring turning on and off one of the I/O lines in rapid succession to properly "clock out" each individual bit, including start bits, stop bits, and parity bits. Because of the integrated serial port we can easily send & receive data, controller takes care of the SERIAL PROTOCOL i.e. sending each bit. All we have to do is to configure the serial port operation mode & the baud rate. And once these settings are made the controller will let us know when it has finished sending the byte that we had written in SBUF (Serial Buffer) as well as when it has received a new byte we just have to write the byte that we have to send in the SBUF or read the received byte from the SBUF

The transmit data pin (TXD) is specified at P3.1, and the receive data pin (RXD) is at P3.0. The serial signals provided on these pins are TTL signal and must be boosted and inverted through a suitable converter (MAX 232) to comply with RS232 standard.

6.2 SCON REGISTER
The SCON SFR allows us to configure the serial port. I won’t go into much details about the SCON SFR but if you want to know about it please check over here. Basically there are four modes we will be using MODE 1 which is a 9 bit UART mode consisting of start bit (0), 8 data bits (LSB first), a parity bit, and a stop bit (1). We will be loading 50h into the SCON SFR (MOV SCON,#50h).

RS232C:

The example serial waveforms in Fig 7.d show the waveform on a single conductor to transmit a byte (0x41) serially. The upper waveform is the TTL-level waveform seen at the transmit pin of 8051. The lower waveform shows the same waveform converted to RS232C levels. The voltage levels of the RS232C are used to assure error-free transmission over greater distances than would be possible with TTL levels.

As shown in Fig 1, each byte is preceded by a start bit and followed by one stop bit. The start and stop bits are used to synchronize the serial receivers. The data byte is always transmitted least-significant-bit first. For error checking it is possible to include a parity bit as well, just prior to the stop bit. The bits are transmitted at specific time intervals determined by the baud rate of the serial signal. The baud rate is the reciprocal of the time to send 1 bit. Error-free serial communication requires that the baud rate, number of data bits, number of stop bits, and presence or absence of a parity bit be the same at the transmitter and at the receiver.

6.3 PROS AND CONS OF SERIAL COMMUNICATION OVER PARALLEL COMMUNICATION
The concept of serial communication is simple, in serial communication data is sent one bit at a time. Although this is slower than parallel communication, which allows the transmission of an entire byte at once, it is simpler and can be used over longer distances.
Typically, serial is used to transmit ASCII data.

7. Applications of 8051 Microcontroller

A Microcontroller has a CPU (a microprocessor) in addition to a fixed amount of RAM, ROM, I/O ports, and a timer all on a single chip.
In other words, the processor, the RAM, ROM, I/O ports and the timer are all embedded together on one chip; therefore, the designer cannot add any external memory, I/O ports, or timer to it.

The fixed amount of on-chip ROM, RAM, and number of I/O ports in Microcontrollers makes them ideal for many applications in which cost and space are critical.

Microcontrollers for Embedded Systems
An embedded system is an application that contains at least one programmable computer (typically in the form of a microcontroller, a microprocessor or digital signal processor chip) and which is used by individuals who are, in the main, unaware that the system is computer-based.
An embedded system product uses a microprocessor (or Microcontroller) to do one task only. A printer is an example of embedded system since the processor inside it performs one task only; namely getting the data and printing it. In an Embedded system, there is only one application software that is typically burned into ROM.

The most important question...Why we should use Atmel Micro-controller?

Why Atmel Devices

Atmel's flash memory is very high.

Without caring about EPROM erases, we can program/reprogram the device during prototype development and most of the time device stays cool even after many hours of running.

Also we can go upto 24MHz with these devices using 3V to 6V supply.

Atmel 89C52/89S52 Microcontrollers

The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer and AT89S52.

It has 4 Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM).

The device is manufactured using Atmel's high density nonvolatile memory technology and is compatible with the industry standard MCS-51Ô instruction set and pinout.

Atmel AT89C52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.

Key Parameters-                    ParameterValue
Flash (Kbytes): 8 Kbytes
Max. Operating Frequency: 24 MHz
CPU:         8051-12C
Max I/O Pins: 32
UART:         1
SRAM (Kbytes):     0.25
Operating Voltage (Vcc): 4.0 to 5.5
Timers:      3
ISP: SPI
Watchdog: Yes

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